A conventional semiconductor device with a multilayer wiring structure has been designed to reduce the wiring resistance of a wiring corresponding to a critical path to enhance the operation speed of a circuit. For example, to reduce the wiring resistance to decrease the wiring delay, it is suggested that the wiring width of a critical path is made wider than the wiring other than the critical path. Also, it is suggested that a plurality of via-holes for connecting between two wiring layers which are formed up and down overlapping with each other are provided to give the same potential therebetween to enlarge the effective wiring sectional area.
However, when the wiring width is enlarged as in the former, there is a problem that it obstructs the miniaturization of wiring thereby reducing the integration density. In this case, the critical path may be formed on a top layer where it is relatively easy to obtain a space for forming the wiring pattern. However, the via-holes for electrically conducting to the critical path on the top layer may cause the increase in wiring resistance or limit the wiring design. In addition, when the number of the critical path becomes large, more layers may be required to further increase the number of steps in the process.
On the-other hand, when a plurality of wiring layers are arranged to have the same potential as in the latter, the wiring for providing the same potential needs to be formed on the top layer. Therefore, the space to form a wiring pattern on the top layer is thereby limited and the total integration density may be reduced. Further, to form the top layer wiring needs the process by the photolithography with using the same mask pattern as the lower critical path wiring as well as the process for forming the via-holes to electrically conduct these wirings. Thus, the number of steps in the process must be very large.